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19-1560; Rev 0; 10/99
+2.7V to +5.5V, Low-Power, Triple, Parallel 8-Bit DAC with Rail-to-Rail Voltage Outputs
General Description
The MAX5101 parallel-input, voltage-output, triple 8-bit digital-to-analog converter (DAC) operates from a single +2.7V to +5.5V supply and comes in a space-saving 16-pin TSSOP package. Internal precision buffers swing Rail-to-Rail(R). For all three DACs, the internal reference voltage is tied to VDD. The MAX5101 has separate input latches for each of its three DACs. Data is transferred to the input latches from a common 8-bit input port. The DACs are individually selected through address inputs A0 and A1 and are updated by bringing WR low. The MAX5101 features a 1A software shutdown mode, as well as a power-on reset mode that resets all registers to code 00 hex on power-up. o Ultra-Low Supply Current 0.3mA while Operating 1A in Software Shutdown Mode o Ultra-Small 16-Pin TSSOP Package o Output Buffer Amplifiers Swing Rail-to-Rail o Power-On Reset Sets All Registers to Zero
Features
o +2.7V to +5.5V Single-Supply Operation
MAX5101
Applications
Digital Gain and Offset Adjustment Programmable Attenuators Portable Instruments Power-Amp Bias Control
PART MAX5101AEUE MAX5101BEUE
Ordering Information
TEMP. RANGE -40C to +85C -40C to +85C PINPACKAGE 16 TSSOP 16 TSSOP INL (LSB) 1 2
Functional Diagram
TOP VIEW
INPUT LATCH A DAC A OUTA
Pin Configuration
OUTB 1 OUTA 2
D0-D7 INPUT LATCH B DAC B OUTB
16 OUTC 15 GND 14 A0
VDD 3 WR 4
MAX5101
13 A1 12 D0 11 D1 10 D2 9 D3
INPUT LATCH C
DAC C
OUTC
D7 5 D6 6 D5 7
A0 A1
CONTROL LOGIC
D4 8
MAX5101
TSSOP
WR
Rail-to-Rail is a registered trademark of Nippon Motorola, Ltd. ________________________________________________________________ Maxim Integrated Products 1
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+2.7V to +5.5V, Low-Power, Triple, Parallel 8-Bit DAC with Rail-to-Rail Voltage Outputs MAX5101
ABSOLUTE MAXIMUM RATINGS
VDD to GND ..............................................................-0.3V to +6V D_, A_, WR to GND ..................................................-0.3V to +6V OUT_ to GND ...........................................................-0.3V to VDD Maximum Current into Any Pin .........................................50mA Continuous Power Dissipation (TA = +70C) 16-Pin TSSOP (derate 5.7mW/C above +70C) ..........457mW Operating Temperature Range MAX5101_EUE .................................................-40C to +85C Maximum Junction Temperature .....................................+150C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10sec) .............................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = +2.7V to +5.5V, RL = 10k, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VDD = +3V and TA = +25C.) PARAMETER STATIC ACCURACY Resolution Integral Nonlinearity (Note 1) Differential Nonlinearity (Note 1) Zero-Code Error Zero-Code-Error Supply Rejection Zero-Code Temperature Coefficient Gain Error (Note 2) Gain-Error Temperature Coefficient DAC OUTPUTS Output Voltage Range DIGITAL INPUTS Input High Voltage Input Low Voltage Input Current Input Capacitance DYNAMIC PERFORMANCE Output Voltage Slew Rate Output Settling Time (Note 3) Channel-to-Channel Isolation (Note 4) Digital Feedthrough (Note 5) VIH VIL IIN CIN From code 00 to code F0 hex To 1/2LSB, from code 10 to code F0 hex Code 00 to code FF hex Code 00 to code FF hex VIN = VDD or GND 10 0.6 6 500 0.5 VDD = 2.7V to 3.6V VDD = 3.6V to 5.5V 2 3 0.8 1.0 V V A pF V/s s nVs nVs RL = 0 VDD V INL DNL ZCE MAX5101A MAX5101B Guaranteed monotonic Code = 00 hex Code = 00 hex, VDD = 2.7V to 5.5V Code = 00 hex Code = F0 hex Code = F0 hex 0.001 10 1 8 1 2 1 20 10 Bits LSB LSB mV mV V/C % LSB/C SYMBOL CONDITIONS MIN TYP MAX UNITS
2
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+2.7V to +5.5V, Low-Power, Triple, Parallel 8-Bit DAC with Rail-to-Rail Voltage Outputs MAX5101
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +2.7V to +5.5V, RL = 10k, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VDD = +3V and TA = +25C.) PARAMETER Digital-to-Analog Glitch Impulse Wideband Amplifier Noise Shutdown Recovery Time Time to Shutdown POWER SUPPLIES Power-Supply Voltage Supply Current (Note 6) Shutdown Current DIGITAL TIMING (Figure 1) (Note 7) Address to WR Setup Address to WR Hold Data to WR Setup Data to WR Hold WR Pulse Width tAS tAH tDS tDH tWR 5 0 25 0 20 ns ns ns ns ns VDD IDD 2.7 280 1 5.5 520 3 V A A tSDR tSDN To 1/2LSB of final value of VOUT IDD < 5A SYMBOL CONDITIONS Code 80 hex to code 7F hex MIN TYP 90 60 13 20 MAX UNITS nVs VRMS s s
Note 1: Reduced digital code range (code 00 hex to code F0 hex) due to swing limitations when the output amplifier is loaded. Note 2: Gain error is: [100 (VF0,meas - ZCE - VF0,ideal) / VDD]. Where VF0,meas is the DAC output voltage with input code F0 hex, and VF0,ideal is the ideal DAC output voltage with input code F0 hex (i.e., VDD * 240 / 256). Note 3: Output settling time is measured from the 50% point of the falling edge of WR to 1/2LSB of VOUT's final value. Note 4: Channel-to-Channel Isolation is defined as the glitch energy at a DAC output in response to a full-scale step change on any other DAC output. The measured channel has a fixed code of 80 hex. Note 5: Digital Feedthrough is defined as the glitch energy at any DAC output in response to a full-scale step change on all eight data inputs with WR at VDD. Note 6: RL = , digital inputs at GND or VDD. Note 7: Timing measurement reference level is (VIH + VIL) / 2.
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+2.7V to +5.5V, Low-Power, Triple, Parallel 8-Bit DAC with Rail-to-Rail Voltage Outputs MAX5101
ADDRESS tAS WR ADDRESS VALID tWR tAH-
tDSDATA SEE NOTE 7, ELECTRICAL CHARACTERISTICS DATA VALID
tDH-
Figure 1. Timing Diagram
__________________________________________Typical Operating Characteristics
(VDD = +3V, RL = 10k, CL = 100pF, code = FF hex, TA = +25C, unless otherwise noted.)
DAC ZERO-CODE OUTPUT VOLTAGE vs. SINK CURRENT
MAX5101-01
DAC FULL-SCALE OUTPUT VOLTAGE vs. SOURCE CURRENT
MAX5101-02
SUPPLY CURRENT vs. TEMPERATURE
MAX5101-03
1.2 1.0 0.8 VOUT (V) 0.6 0.4 0.2 0 0 2 4 6 8 VDD = 5V
10
260 240 SUPPLY CURRENT (A) 220 VDD = 3V; CODE = F0 HEX 200 180 160 140 1 DAC AT CODE 00 OR F0 2 DACs AT CODE 00 (RL = ) -40 -20 0 20 40 60 80 VDD = 5V; CODE = 00 HEX VDD = 3V; CODE = 00 HEX VDD = 5V; CODE = F0 HEX
8
VOUT (V)
VDD = 3V
6 VDD = 5V 4 VDD = 3V 2
0 10 0 2 4 6 8 10 SINK CURRENT (mA) SOURCE CURRENT (mA)
100
TEMPERATURE (C)
WORST-CASE 1LSB DIGITAL STEP CHANGE (NEGATIVE)
MAX5101-04
WORST-CASE 1LSB DIGITAL STEP CHANGE (POSITIVE)
DAC CODE FROM 7F TO 80 HEX
MAX5101-05
DAC CODE FROM 80 TO 7F HEX
CH1
CH1
CH2 CH2
2s/div CH1 = WR, 2V/div CH2 = VOUTA, 50mV/div, AC-COUPLED
2s/div CH1 = WR, 2V/div CH2 = VOUTA, 50mV/div, AC-COUPLED
4
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+2.7V to +5.5V, Low-Power, Triple, Parallel 8-Bit DAC with Rail-to-Rail Voltage Outputs
Typical Operating Characteristics (continued)
(VDD = +3V, RL = 10k, CL = 100pF, code = FF hex, TA = +25C, unless otherwise noted.)
MAX5101
DIGITAL FEEDTHROUGH GLITCH IMPULSE (0 TO 1 DIGITAL TRANSMISSION)
MAX5101-06
DIGITAL FEEDTHROUGH GLITCH IMPULSE (1 TO 0 DIGITAL TRANSMISSION)
MAX5101-07
POSITIVE SETTLING TIME
DAC CODE FROM 10 TO F0 HEX
MAX5101-08
CH1 CH2
CH1 CH2
CH1
CH2 0 TO 1 DIGITAL TRANSITION ON ALL DATA BITS (WITH WR HIGH) 200ns/div CH1 = D7, 2V/div CH2 = VOUTA, 1mV/div, AC-COUPLED 1 TO 0 DIGITAL TRANSITION ON ALL DATA BITS (WITH WR HIGH) 200ns/div CH1 = D7, 2V/div CH2 = VOUTB, 1mV/div, AC-COUPLED CH1 = WR, 2V/div CH2 = VOUTA, 2V/div 1s/div
NEGATIVE SETTLING TIME
MAX5101-09
INTEGRAL AND DIFFERENTIAL NONLINEARITY vs. DIGITAL CODE
0.4 0.3 0.2 INL/DNL (LSB) DNL RL =
MAX5101-10
0.5
DAC CODE FROM F0 TO 10 HEX
CH1
0.1 0 -0.1 -0.2
CH2
-0.3 -0.4 -0.5 1s/div CH1 = WR, 2V/div CH2 = VOUTA, 2V/div 0 32 64 96
INL
128 160 192 224 256
DIGITAL CODE
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+2.7V to +5.5V, Low-Power, Triple, Parallel 8-Bit DAC with Rail-to-Rail Voltage Outputs MAX5101
Pin Description
PIN 1 2 3 4 5-12 13 14 15 16 NAME OUTB OUTA VDD WR D7-D0 A1 A0 GND OUTC DAC B Voltage Output DAC A Voltage Output Positive Supply Voltage. Bypass VDD to GND using a 0.1F capacitor. Write Input (active low). Use WR to load data into the DAC input latch selected by A0 and A1. Data Inputs 7-0 DAC Address Select Bit (MSB) DAC Address Select Bit (LSB) Ground DAC C Voltage Output FUNCTION
Detailed Description
Digital-to-Analog Section
The MAX5101 uses a matrix decoding architecture for the digital-to-analog converters (DACs). The internal reference voltage is connected to VDD and divided down by a resistor string placed in a matrix fashion. Row and column decoders select the appropriate tab from the resistor string to provide the needed analog voltages. The resistor network converts the 8-bit digital input into an equivalent analog output voltage in proportion to the supply voltage (VDD). The resistor string presents a code-independent input impedance to the supply and guarantees a monotonic output. The voltages are buffered by rail-to-rail op amps connected in a follower configuration to provide a rail-to-rail output (see Functional Diagram).
Digital Inputs and Interface Logic
In the MAX5101, address lines A0 and A1 select the DAC that receives data from D0-D7, as shown in Table 1. When WR is low, the addressed DAC's input latch is transparent. Data is latched when WR is high. The DAC outputs (OUTA, OUTB) represent the data held in the three 8-bit input latches. To avoid output glitches in the MAX5101, ensure that data is valid before WR goes low.
Low-Power Shutdown Mode
The MAX5101 features a software shutdown mode. A write performed to address A1 = H and A0 = H causes the device to shut down. A subsequent write to any of the other three addresses disables shutdown and turns the analog circuitry on. As the MAX5101 comes out of shutdown, all registers retain their digital values prior to shutdown. However, when the device powers up (i.e., VDD ramps up), all latches are internally preset with code 00 hex. In shutdown, the output amplifiers enter a high-impedance state. When bringing the device out of shutdown, allow 13s for the output to stabilize.
Output Buffer Amplifiers
The DAC outputs are internally buffered by a precision amplifier with a typical slew rate of 0.6V/s. The typical settling time to 1/2LSB at the output is 6s when loaded with 10k in parallel with 100pF.
Power-Supply Bypassing and Ground Management
Digital or AC transient signals on GND can create noise at the analog output. Return GND to the highest-quality ground available. Bypass VDD with a 0.1F capacitor, located as close to VDD and GND as possible. Careful PC board ground layout minimizes crosstalk between the DAC outputs and digital inputs.
DAC Reference Voltage
The MAX5101's reference is internally tied to VDD. The output voltage (VOUT) for any DAC is represented by a digitally programmable voltage source as follows: VOUT = (NB * VDD) / 256 where NB is the numeric value of the DAC binary input code.
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+2.7V to +5.5V, Low-Power, Triple, Parallel 8-Bit DAC with Rail-to-Rail Voltage Outputs
Table 1. MAX5101 Addressing Table (partial)
WR H L L L L A1 X L L H H A0 X L H L H OPERATION Input data latched DAC A input latch transparent DAC A input latch transparent DAC A input latch transparent Enter shutdown mode
Chip Information
TRANSISTOR COUNT: 6848
MAX5101
H = high state, L = low state, X = don't care
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+2.7V to +5.5V, Low-Power, Triple, Parallel 8-Bit DAC with Rail-to-Rail Voltage Outputs MAX5101
Package Information
TSSOP.EPS
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
8 _____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 1999 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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